1. Field of the Invention
The present invention relates to the field of operational amplifiers.
2. Prior Art
Key performance specifications of operational amplifiers are its input referred offset and noise voltages. These are usually specified as single error sources at the input of the amplifier.
FIG. 1 shows a typical prior art folded cascode operational amplifier. Its input referred offset voltage Vos is mainly due to the offset voltages between matched transistor pairs M1-M2, M3-M4 and M6-M7. These offset voltages can be calculated back to the input as
                              Vos          =                      Δ            ⁢                                                  ⁢            V            ⁢                                                  ⁢            1                          ,                  2          +                                                                      Gm                  ⁢                                                                          ⁢                  3                                ,                4                                                              Gm                  ⁢                                                                          ⁢                  1                                ,                2                                      ⁢            Δ            ⁢                                                  ⁢            V            ⁢                                                  ⁢            3                          ,                  4          +                                                                      Gm                  ⁢                                                                          ⁢                  6                                ,                7                                                              Gm                  ⁢                                                                          ⁢                  1                                ,                2                                      ⁢            Δ            ⁢                                                  ⁢            V            ⁢                                                  ⁢            6                          ,        7                            (        1        )            
Where ΔV and Gm are the offset voltages and transconductances of the indicated transistors. M8-M9 and M10-M11 are cascode devices and therefore do not contribute significantly to Vos.
The input referred RMS voltage noise Vnin can be calculated from
                                                        Vn              in              2                        =                                          V                n                            ⁢                              1                2                                              _                +                                            V              n                        ⁢                          2              2                                _                +                                            (                                                Gm                  ⁢                                                                          ⁢                  3                                                                      Gm                    ⁢                                                                                  ⁢                    1                                    ,                  2                                            )                        2                    ⁢                                                    V                n                            ⁢                              3                2                                      _                          +                                            (                                                Gm                  ⁢                                                                          ⁢                  4                                                                      Gm                    ⁢                                                                                  ⁢                    1                                    ,                  2                                            )                        2                    ⁢                                                    v                n                            ⁢                              4                2                                      _                          +                                  ⁢                                            (                                                Gm                  ⁢                                                                          ⁢                  5                                                                      Gm                    ⁢                                                                                  ⁢                    1                                    ,                  2                                            )                        2                    ⁢                                                    v                n                            ⁢                              5                2                                      _                          +                                            (                                                Gm                  ⁢                                                                          ⁢                  6                                                                      Gm                    ⁢                                                                                  ⁢                    1                                    ,                  2                                            )                        2                    ⁢                                                    v                n                            ⁢                              6                2                                      _                                              (        2        )            
Where Vni is the RMS voltage noise of each contributing transistor. Similar to Vos, it can be assumed that the noise voltages from cascode devices M8-M11 do not add to Vnin.
To minimize both Vos and Vin, the transconductance of the input stage Gm1,2 should be maximized and the transconductances of the transistors in the folding stage M3-M6 should be minimized. This is traditionally done by choosing the W/L ratios such that M1 and M2 operate in weak inversion and M3-M6 operate in strong inversion. Further decreasing the transconductances of M3-M6 by lowering their drain currents is usually not done as it deteriorates the slewrate of the amplifier.
In strong inversion the Gm of a MOS transistor is defined as
                              G          m                =                              2            ⁢                          I              d                                            V                          gs              ,              eff                                                          (        3        )            where Id is the drain current and Vgs,eff is the effective gate-source voltage or gate-source voltage Vgs minus threshold voltage Vt. The transconductance in weak inversion is
                              G          m                =                              I            d                                nV            th                                              (        4        )            where n is the weak inversion slope factor with an approximate value of 2 and Vth is the thermal voltage kT/q which is about 25 mV at room temperature.
As an example, consider the offset voltages in the input transistor pair to be 5 mV and in transistor pairs M3-M4 and M5-M6 to be 10 mV. To maintain good bandwidth in the folding stage, transistors M3-M6 have a much smaller area than M1-M2 and therefore have larger offset voltages. Vgs,eff is in the order of 100 mV. Much more effective gate-source voltage is usually not allowed as it increases the minimum supply voltage the circuit can operate at and limits the common mode input voltage range. Vos is then
      5    ⁢                  ⁢    mV    +      5    ⁢                  ⁢    mV    +                    5        ⁢                                  ⁢        mV            2        .  
It can be seen that the contributions to Vos from the offset voltages in transistor pairs M3-M4 and M5-M6 are in the same order as that from input pair M1-M2.
The noise of a MOS transistor is defined as
                                                        Vn              2                        _                                Δ            ⁢                                                  ⁢            f                          =                              4            ⁢            kT            ⁢                          2              3                        ⁢                          1              Gm                                +                      K            ⁢                                                  ⁢                                                            I                  a                                ⁢                D                                            Gm                                  2                  f                                                                                        (        5        )            where k is the Boltzman constant, T is the temperature, K is a constant for a given device and a is a constant between 0.5 and 2. The first term on the right hand side of formula 5 is the thermal noise component, and the second term is the flicker noise component. The transconductance of an NMOS transistor is about 3 times that of a PMOS transistor when both operate under the same conditions. Also, flicker noise in NMOS devices is usually much larger than in PMOS devices. Substituting (5) into (2) for each individual transistor results in the noise sources from M3 and M4 to be dominant in the circuit.